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CUSTOMER PROCUREMENTSPECIFICATION
216COl/CO2
CPUCENTRALPROCESSINGUNIT
FEATURES
Part
Zi 6COl
Z16CO2
Memory Address 8 Mbytes 64 Kbytes
Memory Extension 48 Mbytes 384 Kbytes
Speed (MHz) 10 10
H 1 n n H n
Extendable Register Files Nine Basic Instruction Types Eight User-Selectable Addressing Modes Seven Data Types Supports Three Interrupt Types and Four Traps RISC-Like Load/Store Architecture
n n n n
40/48-Pin PDIP and 44-Pin PLCC Packages' +4.5 I V,, I +5.5-Volt Operating Range Low-Power CMOS 0C to +70C Temperature Range
GENERAL DESCRIPTION
The Z16COl/CO2 CPU are members of the 16-bit processor and controller family. Designed using a RISC-like Load/Store architecture, the CPU can operate in either system or normal modes, permitting privileged operations and improving operating system organization and implementation. To boost the main CPU' performance capability, the s processor core includes hardwired control and is a 16-bit real-time processor functioning at register access speeds. Register flexibility is created by grouping or overlapping multiple registers, and by allowing extended register file capabilities as the system expands. Easy extended register file control is accomplished through a single instruction stream communication. TheCPUsupportsthreetypesof interrupts (non-maskable, vectored, and non-vectored) and four traps (system call, extended process architecture instruction, privileged instructions, and segmentation trap). The vectored and non-vectored interrupts are maskable. The processor' resources include seven data types that s range from bits to 32-bit long words, and byte and word strings, plus eight user-selectable addressing modes. The nine basic instruction types can be combined with various data types and addressing modes to form a powerful set of 414 instructions. The extended processing architecture features provide a modular approach to expanding both the hardware and software capabilities of the Z16COl/CO2.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.: B/AN(WORDis active Low); /B/W^(BYTE is active Low, only). Powerconnections follow conventionaldescriptions below:
Connection Power Ground Circuit "cc GND Device V DO "ss
cPs95scc0103
(3/95)
1
~ziLfli5
GENERAL DESCRIPTION (Continued)
216CWCO2 +cPs95sccolo3
internal Data Bus 0
Z-Bus Z-Bus Interface
Z16COO CPU Functional Block Diagram
AD13 c) AD14 c) AD13 c) AD12 c) REAMWRITE hwlM4u/sYsTEM BYTEWORD 3laius ~573 ~ST2 ST1 zid~i YBw" AD11 c) AD10 c) ADi ,AM).AD? ,c) A06 .A& AM .A03
3m
IWAlT /STOP
.-
A02 .AD1 ,AW -
iNMI lnlemlpN M INVI
: : : :
sN4 sN2 sN2 SNl
Z16COVCO2 Signal Descriptions
2
Z16COlKO2 cPs95scc0103
PIN DESCRIPTION
AD6 SN6 SN5 AD7 AD6 AD4 SN4 AD5 AD3 iD2 AD1 sN2 GND CLOCK IAS NIC ww Nils WIW BUSACK IWAIT /BUSREP SNO
216CO2 40-Pin PDIP 216COl 46-Pin PDIP
SNI
Z16CO2 44-Pin PLCC
3
Z16COlKO2 + cPs95scc0103
ABSOLUTE MAXIMUM RATINGS
Voltages on V,, with respect to V,, . ... . .. .. . . .. .-0.3V to +7.OV Voltages on all inputs with respect to Vss........""............................................. -0.3V to V,,+O.3V Storage Temperature.. .... ...... .... .. ..... .... .. ... .-65"C to + 150% Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operating of the device at any condition above these indicated in the operational sectionsof these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The DC characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into the referenced pin. Available operating temperature ranges are: s = 0C to +7O"C, + 4.5v s V,,I (Z16COi,Zl6CO2) E = -4OOC to +lOO"C, + 4.5V IV& (Z16CO1, Zi 6CO2) + 5.5v + 5.5V All AC parameters assume a total load capacitance (including parasitic capacitances) or 100 pf max, except for parameter 6 (50 pf max). Timing reference between two output signals assume a load difference of 50 pf max. The Ordering Information section lists package temperature ranges and product numbers.
DC CHARACTERISTICS SYm
VCH VCL Parameter MIN v&I.4 -0.3 2.0 2.4 2.4 -0.3 2.4 -100 MAX v,,to.3 0.45 v,,to.3 v,$o.3 v,,tD.3 0.8 0.4 L-10 100 *lo 35 Units v v v v v V V I"J\ f#I p4 rnA Condition Drivenby External ClockGenerator Drivenby External ClockGenerator
ClockinputHighVoltage ClockinputLowVoltage InputHighVoltage VI, V,, RESET InputHighVoltage /RESET on Pin V,, NMI InputHighVoltage NMI Pin on InputLowVoltage Vi, VOH OutputHighVoltage VOL OutputLowVoltage I InputLeakage I\ SEGT InputLeakage /SEGT on Pin IOL OutputLeakage V,, Power SupplyCurrent ICC
I,,=-250uA b:4;` :$ +2.4V
0.4V< VIN< t2.4V 10MHz
4
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FOOTNOTES TO AC CHARACTERISTICS
ZlGCOlR 10 MHz Equation _ 2TcCtTwCh-6On.s TwClt5ns TcCtTwCh-3Ons TwCh-20ns TcC-20ns TwCI-20ns TwCh-25ns 2TcC-60ns TwCh-20ns 2TcG60ns * TwCI-20ns TwCh-5n.s TwCI-7Ons TwCEns TcCtTwCh-6Ons TwCI-15ns TcC-35ns TcCtTwCh-3Ons TcC-25n.s 2TcC-80ns 2TcC-40ns 4TcCtTwCI-30ns 2TcCtTwCh-75ns TwCh-20ns TcCSOns TwCI-1Ons
Z16GOllCO2 cPs95sccolo3
'
No. 11 13 16 17 19 20 21 22 25 27 28 29 30 32 33 35 36 38 40 41 43 44 46 48 68 69
Symbol TdA(DR) TdDS(A) TdDW(DS) TdA(MR) TwMRh TdMR(A) TdDW(DSW) TdMR(DR) TdA(AS) TdAS(DR) TdDS(AS) TwAS TdAS(A) TdAS(DSR) TdDSR(DR) TdDS(DW) TdA(DSR) TwDSR TwDSW TdDSI(DR) TwDS TdAS(DSA) TdDSA(DR) TdS(AS) TWA TdDS(s)
'
ACTimingTestConditions: VoL= 0.8V VOH= 2.ov 'I,,= 0.8V V,,= 2.4V v,,, =0.45v yHc= v,, - 0.4v
,
Zl6COlKO2 cPs95sccolo3
AC CHARACTERISTICS
216CO1/2 10 MHz Min Max 100 40 40 ** ** ** 10 10 50 50 50 50 180 20 45* 60 0 110* 20 50 80 20 15* 140* 50 35 20 25 140 20* 35* 30 0 35* 80 30 25* 65* 45 110* 45 75* 120* 45 160 410* 45 165* 50
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Symbol
Parameter
TcC ClockCycleTime TwCh ClockWidth(High) TwCl ClockWidth(Low) ClockFallTime TfC TrC ClockRiseTime Number Valid(50pfload) TdC(SNv) Clock+Segment TdC(SNn) Clocktsegment Number Valid Not TdC(Bz) , Clockt Bus Float TdC(A) ClocktAddressValid TdC(Az) TdA(DR) TsDR(C) TdDS(A) TdC(DW)' ThDR(DS) TdDW(DS) TdA( MR) TdC(MR) TwMRh Clock+ Address Float Address Validto Read Required Data Valid Read to ClockFallSetupTime Data /DStAddressActive Clock+ WriteDataValid ReadDatato /DS RiseHoldTime WriteDataValidto /DS RiseDelay Address Validto /MREQFallDelay ClockFallto /MREQFallDelay /MREQ Width(High)
0
Not TdMR(A) /MREQ[ Address Active TdDW(DSW)WriteDataValidto /DS Fall(Write)Delay Valid TdMR(DR) /MREQ[ReadDataRequired ClockFall/MREQRiseDelay TdC(MR) TdC(ASf) Clock+ /AS Fall Delay Address Validto /AS RiseDelay TdA(AS) TdC(ASr) Clock[ /AS RiseDelay TdAS( DR) /AS + ReadDataRequired Valid TdDS(AS) /DS + /AS Fall Delay TwAS /AS Width(Low) /AS t Address ActiveDelay Not TdAS(A) Floatto /DS (Read) Delay Fall TdAz(DSR) Address Fall TdAS(DSR) /AS t /DS (Read) Delay Fall Data Valid TdDSR(DR) /DS (Read) to Read Required ClockFallto /OS RiseDelay TdC(DSr) TdDS(DW) /DS + WriteDataNotValid Validto /DS (Read) Delay Fall TdA( DSR) Address Fall TdC(DSR) ClockRise/DS (Read) Delay TwDSR /DS (Read) Width(Low) TdC(DSWj ClockFallto /DS (Write)FallDelay TwDSW TdDSI(DR) TdC(DSf) TwDS TdAS(DSA) TdC(DSA) TdDSA(DR) TdC(S) /DS (Write)Width(Low) /DS (l/O) [ Read Required Data Valid Clock [ /DS (l/O) FallDelay /DS (l/O) Width(Low) /AS t /DS (Acknowledge) Delay Fall Clock+ /DS (Acknowledge) Delay Fall /DS (Acknowledge)ReadDataRequired [ Delay ClockRiseto Status ValidDelay
6
I ~ZllJJE Zl6COllCO2 cPs95sccolo3
AC CHARACTERISTICS
(Continued)
216CO112 10 MHz Min Max , 20* 35 0 35 35 35 10 35 10 35 0 50 35 0 20 5 35 5 35 35 ,. 50* 30
No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Symbol TdS(AS) TSR(C) ThR(C) TwNMl TsNMI(C) TsVI(C) ThVI(C) TsSGT(C) ThSGT(C) TsMI(C) ThMI(C) TdC(M0) TsSTP(C) ThSTP(C) TsW(C) ThW(C) TsBRQ(C) ThBRQ(C) TdC(BAKr) TdC(BAKf) TWA TdDS(S)
Parameter Status Validto /AS RiseDelay /RESET ClockRiseSetupTime to /RESET ClockRiseHoldTime to /NMI Width(Low) /NMIto ClockRiseSetupTime /VI, /NVIto ClockRiseSetupTime /VI, /NVIto ClockRiseHoldTime /SEGT ClockRiseSetupTime to /SEGT ClockRiseHoldTime to /Mt to ClockRiseSetupTime /MI to ClockRiseHoldTime . ClockRiseto /MO Delay /STOP ClockFallSetupTime to /STOP ClockFallHoldTime to /WAITto ClockFallSetupTime /WAITto ClockFallHoldTime /BUSREQ ClockRiseSetupTime to /BUSREQ ClockRiseHoldTime, to ClockRiseto /BUSACK Delay Rise ClockRiseto /BUSACK Delay Fall Address Width Valid /DS Riseto STATUS Valid Not
* Clock-cycle time-dependent characteristics. Footnotes AC Characteristics. See to ** Clockmaybe stopped. t Unitsin nanoseconds (ns).
"
," 7
--
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COMPOSITE AC TIMING DIAGRAM
Zl6COllCO2 cPs95sccolo3
This composite liming dia. gram does not show actual timing sequences. Refer to this diagram only for the detailed timing relationships of indiwdual edges. Use the precedtng illustrations as an exolanation of the various iitiing sequences.
Trming measurements are made al the followrng voltages. U.^. I ^... Clock oulput input FlOal 4.ov 2.ov 2.ov V D.8V 0.8V 0.8V rD.5V
DATA IN
n
I
Y-READ
INTERRUPT ACKNOWLEWE
Composite AC liming 6
216COllCO2 cPs95scc0103
TIMING DIAGRAMS
i -5
\
i I 1 I I I
.E E .I% 8 u
216COllCO2' cPs95scc0103
TIMING DIAGRAMS (Continued)
'
WAIT
CTCLES
ADDEC
(-` ")
.I
C
I
8s IUWT
uw IDIWT
T
. ` ADDRESS co(lT
w OUTWT DATA OUT
.
II II
x
I I
J
Input/Output Timing
Y-t-t10
L
Z16COVCO2 cPs95sccolo3
TIMING DIAGRAMS (Continued)
maL
i
.
@b-we
$c
i
u. Ix II
Y
<
191
Interrupt and Segment Trap Request/Acknowledge liming
-
11
Z16COlKO2 cPs95scc0103
TIMING DIAGRAMS (Continued)
4
CLOCU
AH CVCLLS ADDED iiD
Iii
/
AD MAD
YDW ABMESS
)--
(Z)
S MAO
ns WNHE I
Memory Read and Write Timing
Zi 6COWO2 cPs95scc0103
TIMING DIAGRAMS (Continued)
-E
AVWLL-
J
J
;..
;..
/
/
AD
Bus Request/Acknowledge
Timing
13
Zl6COl/C42 * ; cPs95sccolo3 '
TIMING DIAGRAMS (Continued)
'
r
Stop Timing
0 1995 byzilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered bywarrantyand patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog' products are not authorized for use as critical compos nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-8800 Telephone (408) 370-8000 Telex 91 O-338-7821 FAX 408 370-8058 Internet: http://www.zilog.comMlog General Questions: infoOzilog.com
14

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